n->vcpu_info->evtchn_upcall_mask = 1;
regs->entry_vector = TRAP_syscall;
- regs->rflags &= 0xFFFCBEFFUL;
+ regs->rflags &= ~(X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF|
+ X86_EFLAGS_NT|X86_EFLAGS_TF);
regs->ss = __GUEST_SS;
regs->rsp = (unsigned long)(rsp-11);
regs->cs = __GUEST_CS;
movl %eax,UREGS_gs+4(%esp)
nvm86_3:/* Rewrite our stack frame and return to ring 1. */
/* IA32 Ref. Vol. 3: TF, VM, RF and NT flags are cleared on trap. */
- andl $0xfffcbeff,UREGS_eflags+4(%esp)
+ andl $~(X86_EFLAGS_VM|X86_EFLAGS_RF|\
+ X86_EFLAGS_NT|X86_EFLAGS_TF),UREGS_eflags+4(%esp)
mov %gs,UREGS_ss+4(%esp)
movl %esi,UREGS_esp+4(%esp)
movzwl TRAPBOUNCE_cs(%edx),%eax
FLT13: movq %rax,(%rsi) # RCX
/* Rewrite our stack frame and return to guest-OS mode. */
/* IA32 Ref. Vol. 3: TF, VM, RF and NT flags are cleared on trap. */
+ /* Also clear AC: alignment checks shouldn't trigger in kernel mode. */
movl $TRAP_syscall,UREGS_entry_vector+8(%rsp)
- andl $0xfffcbeff,UREGS_eflags+8(%rsp)
+ andl $~(X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF|\
+ X86_EFLAGS_NT|X86_EFLAGS_TF),UREGS_eflags+8(%rsp)
movq $__GUEST_SS,UREGS_ss+8(%rsp)
movq %rsi,UREGS_rsp+8(%rsp)
movq $__GUEST_CS,UREGS_cs+8(%rsp)